(a) Field of the Invention
The present invention relates to a wiring board for use in mounting an electronic component such as a semiconductor device. More particularly, the present invention relates to a wiring board (hereinafter referred to as an “electronic component mounting package” or merely as a “package”) adapted for mounting an electronic component using a thermosetting material, the wiring board having a structure of a multilayer wiring board in which a plurality of wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through via holes formed in the insulating layer.
(b) Description of the Related Art
Conventionally, build-up process has been widely used as a technology for manufacturing a wiring board of multilayer structure. With the use of the build-up process, a variety of multilayer wiring boards can be fabricated by varying the combination of a material (typically, a thermosetting resin) for an interlayer dielectric and a via hole formation process. A typical manufacturing process for the multilayer wiring board using the build-up process is to repeat, in turn, the formation of an insulating layer, the formation of a via hole in the insulating layer, and the formation of a wiring pattern on the insulating layer and also in the via hole, on both or either one surface of a core substrate serving as a support base member. In such a structure, wiring layers and insulating layers can be thinly formed since the build-up process is used for their stacking, while the core substrate requires an appropriate thickness for affording the wiring board rigidity. This leads to a limitation to making the entire package thinner.
In view of this, a structure without a core substrate serving as a support base member has recently been adopted so as to make a wiring board (package) still thinner. The wiring board of such a structure is also referred to as a “coreless substrate” in the meaning that it has no “core” portion.
Although description is given later for a method of manufacturing such a coreless substrate, the basic process thereof includes: preparing a temporary substrate as a support; forming, in sequence, a desired number of build-up layers (namely, insulating layers including via holes, and wiring patterns including the insides of the via holes) on the temporary substrate; and removing the temporary substrate.
An example of a technology related to the above art is disclosed in Japanese unexamined Patent Publication (Kokai) 2000-323613. The technology disclosed in this publication provides a multilayer wiring board for a semiconductor device, and in the multilayer wiring board, a mounting surface on which a semiconductor device is mounted is formed as flat and thin as possible. Another example of a technology related to the above art is disclosed in JPP (Kokai) 2007-158174. The technology disclosed in this publication provides a method of manufacturing a wiring board (coreless substrate) in which a build-up wiring layer is formed on a temporary substrate so as to be delaminatable therefrom, and the method enables reliable, low-cost manufacturing of a wiring board without any problem.
As mentioned above, the conventional coreless substrate (semiconductor package) has an advantage of allowing a reduction in thickness thereof since it does not need any core substrate. On the other hand, the conventional coreless substrate has a disadvantage of being prone to “warpage” since the absence of the core substrate affords the overall package low rigidity. This problem develops more markedly when a chip is mounted on the substrate.
Specifically, in the chip mounting, bumps (electrode terminals) are firstly formed on a chip to be mounted. Thereafter, the electrode terminals of the chip are electrically connected to pad portions exposed from a chip mounting surface of the coreless substrate, by flip chip bonding. Then, an underfill resin is filled into a gap between the substrate and the chip so as to insulate and shield the connection portions therebetween (the pad portions and the electrode terminals) from the outside. At that time, baking (heat treatment) is performed in order to heat-cure the underfill resin. However, this causes a shrinkage in the underfill resin and in turn leads to warpage in the periphery of the substrate toward the chip mounting surface, due to the fact that the coefficient of thermal expansion of the chip is different from that of the substrate.
Thus, in the structure of the conventional coreless substrate (semiconductor package), the low rigidity of the overall package causes a “warpage” during chip mounting, and this can possibly cause chip delamination, depending on the degree of warpage. Accordingly, the structure has a problem in that reliable chip mounting is impossible with the structure. Neither the above JPP (Kokai) 2000-323613 nor 2007-158174 makes reference to such a problem.
Additionally, the timing of the warpage to occur in the substrate is not limited to only the time of chip mounting, but also the warpage may possibly occur even at stages before chip mounting. For example, in the case where a coreless substrate is delivered and then a chip is mounted thereon, the warpage can possibly occur in the substrate, depending on how the substrate is handled during the processes from the delivery to the mounting, because the coreless substrate is intrinsically low in rigidity and flexible.
Moreover, this problem is not necessarily unique to the coreless substrate and may possibly likewise arise in a build-up multilayer wiring board having the core substrate. Specifically, the coefficient of thermal expansion of a material constituting the wiring layer, such as copper (Cu), is significantly different from that of a material constituting the insulating layer, such as an epoxy resin. Thus, the application of the approach of building up the wiring and insulating layers alternatingly with one on top of another to one surface of the core substrate at given intervals of time (namely, the build-up process) can possibly induce thermal stress at the interface between the wiring layer and the insulating layer in the thickness direction of the layers according to the difference in the coefficient of thermal expansion during the process of building up. As a result, the warpage may occur in the substrate.